Qlaudia

← All courses

AI Infrastructure Fundamentals for Analysts

  • Artificial Intelligence
  • Technology & Computing
  • Business & Finance

Explore the five-layer AI infrastructure value chain—from chips and manufacturing through power, networking, and software—to understand how industry news affects different companies across the ecosystem. Each layer has distinct competitors, economics, and dependencies, so a single headline's impact depends on where a company sits in the stack.

Sign in to enroll$531 lessons

What you'll learn

  • GPUs for AI WorkloadsChips originally designed for rendering images through parallel processing of the same calculation across thousands of simple cores, which turned out to be ideally suited for the matrix multiplication operations underlying modern AI models.
  • Cloud Platforms and Hyperscaler CapexServices that bundle hardware access, systems software orchestration, and developer tools to rent AI compute capacity at scale rather than requiring customers to build their own infrastructure.
  • Interpreting AI Infrastructure NewsA systematic approach to locating news within the AI infrastructure value chain by identifying which layer—chips, manufacturing, memory, or networking—an announcement actually affects, so different impacts across interdependent companies can be properly assessed.
  • Foundry Business ModelA manufacturing company that produces chips according to designs created by other companies, rather than designing and manufacturing its own branded chips.
  • AI Value Chain Structure and Company MappingA framework for categorizing companies by their position in the AI infrastructure chain—such as chip design, manufacturing, packaging, and deployment—to understand each entity's business model and competitive dynamics.
  • Custom AI Accelerators and ASICsChips designed specifically to run one company's particular AI workloads with maximum efficiency, sacrificing flexibility for performance gains at scale.
  • Data Center Power DemandThe sustained, enormous electricity consumption of AI clusters running continuously at high utilization, creating grid constraints and becoming the primary bottleneck limiting how quickly AI infrastructure can scale.
  • High-Bandwidth Memory for AI ChipsA type of DRAM built by stacking memory dies vertically and placing them next to a processor within the same chip package to enable fast data movement between memory and processing units in AI accelerators.
  • Semiconductor Design vs Manufacturing SplitThe separation of chip creation into two distinct businesses where fabless companies design chips while foundries physically manufacture them on silicon wafers.
  • Networking Switch Silicon SuppliersSpecialized, highly differentiated chips that route data packets between servers in AI data centers at extreme speed and scale, requiring engineering sophistication comparable to AI accelerator design despite performing a different function.
  • Scale-Up vs Scale-Out NetworkingTwo distinct network layers where scale-up provides extremely high bandwidth and low latency for chips in the same server or rack, while scale-out connects chips across distant servers and data centers.
  • GPU vs ASIC Competitive DynamicsThe recurring decision faced by major AI computing buyers to choose between general-purpose GPUs from merchant suppliers or invest in custom ASICs tailored to narrower workloads, with the choice driven by factors like deployment scale and workload characteristics.
  • Semiconductor Manufacturing Process OverviewThe physical sequence of steps that transforms refined silicon into finished chips, beginning with wafer creation and continuing through repeated patterning, etching, and layering loops.
  • AI Networking Equipment VendorsCompanies like Arista Networks that build switches, routers, and network software to connect thousands of AI chips within data centers so they can function as a single system.
  • Data Center Physical Buildout TrendsThe construction and design of new facilities purpose-built to house thousands of GPUs or accelerators with the electrical supply, cooling, and density specifications required by modern AI workloads.
  • Contract Manufacturing and System IntegrationThe assembly and integration step that transforms individual silicon chips and components into finished, deployable servers and systems ready for data center installation.
  • Advanced Chip PackagingManufacturing techniques like TSMC's CoWoS that combine multiple processor and memory dies into one tightly integrated package to reduce data travel distance and increase bandwidth in AI accelerators.
  • Advanced Lithography and EUV TechnologyA manufacturing process that transfers circuit patterns onto silicon wafers using increasingly precise light sources, with extreme ultraviolet light enabling smaller and denser transistors than traditional methods.
  • Data Center Cooling SystemsLiquid and air-based systems that remove the extreme heat generated by densely-packed AI hardware, with liquid cooling becoming essential as power densities exceed what air circulation alone can handle.
  • GPU Programming Platforms and CUDASoftware tools including a programming language, compiler, and libraries that enable developers to write code that runs on graphics processing units and leverages their parallel processing architecture.
  • Nuclear and Baseload Power for Data CentersContinuous, weather-independent electricity supply that AI data centers require around the clock to avoid downtime and corrupted workloads, which nuclear power can reliably provide at low carbon intensity.
  • Ultra Ethernet Consortium and Open StandardsAn industry group founded in 2023 by major technology companies to develop Ethernet networking specifications optimized for AI and high-performance computing as a competitive alternative to InfiniBand.
  • InfiniBand vs Ethernet in AI NetworkingA technology shift in AI cluster networking from InfiniBand, originally designed for high-performance computing with very low latency and high throughput, toward Ethernet, the general-purpose networking technology used throughout the broader computing industry.
  • Power Management and Distribution EquipmentSpecialized electrical infrastructure including transformers, switchgear, and backup systems that convert incoming grid power and safely distribute it throughout a data center to individual racks.
  • Memory Market CyclicalityA recurring boom-and-bust pattern in the commodity-like DRAM and NAND memory industry where rising demand triggers simultaneous capacity investments across manufacturers, resulting in supply overshoots that crash prices and subsequently discourage investment until the cycle repeats.
  • Custom Chip Co-Design PartnershipsCollaborations between hyperscalers and specialist design firms like Broadcom that combine knowledge of specific workload requirements with deep engineering expertise to create tailored silicon.
  • Wafer Fabrication EquipmentSpecialized machinery that performs multiple manufacturing steps beyond lithography to build functional chips, including depositing thin material layers and other essential processes across many chip-building stages.
  • AI Frameworks and Developer EcosystemsSoftware toolkits like PyTorch and TensorFlow that allow developers to build and train machine learning models using pre-built components rather than writing low-level code for every mathematical operation.
  • NAND Storage and Data Center MemoryNon-volatile memory technology used for durable, large-scale data storage in AI data centers, serving a fundamentally different purpose than volatile DRAM/HBM which requires constant power and provides ultra-fast temporary working memory for active computation.
  • On-Board Power Delivery ChipsSemiconductors mounted directly on circuit boards that convert and regulate voltage at the precise point where GPUs, CPUs, or memory chips receive power.
  • Enterprise AI Software SuitesCommercial bundles that combine pre-built models, optimized frameworks, orchestration tools, and vendor support to enable businesses to reliably deploy and manage AI workloads in production at scale.

About this course

What This Course Covers

When you read a headline like "Microsoft signs multi-billion-dollar deal for AI data center capacity" or "ASML reports strong EUV lithography bookings," you are reading about two very different parts of the same industrial ecosystem. This course gives you a map of that ecosystem — the AI infrastructure value chain — so you can quickly place any piece of news into its correct location and understand who benefits, who is threatened, and why.

AI infrastructure is not a single product. It is a stack of physical and software layers, each built by different companies with different business models, cost structures, and competitive dynamics. Understanding this stack matters because a single AI-related headline can be bullish for one company and irrelevant — or even bearish — for another company that sits one layer away in the same chain.

Why a Layered View Matters for Analysts

Consider a concrete example: a report that a hyperscaler (a large cloud provider like Microsoft, Google, or Amazon) is designing more of its own custom AI chips. To a generalist, this might read as "bad for AI chip companies." But with a layered view, you know to ask: bad for which chip company? Nvidia, which sells general-purpose AI chips, faces a genuine competitive threat. But Broadcom, which often designs those very custom chips as a partner to the hyperscaler, and TSMC, which manufactures them regardless of who designed them, may see this as good news. The same headline moves through the value chain differently depending on where a company sits.

The Five Layers

The course organizes AI infrastructure into five interconnected layers:

  1. Chips — the silicon that actually performs AI computation: GPUs (general-purpose accelerators) and custom ASICs (application-specific chips), plus the memory that feeds them.
  2. Manufacturing and equipment — the foundries (like TSMC) that physically produce chips, and the specialized equipment makers (ASML, Applied Materials, Lam Research, KLA) whose machines make advanced chip production possible.
  3. Power, cooling, and data centers — the physical facilities and energy infrastructure (utilities like Constellation Energy, equipment makers like Vertiv) required to run thousands of power-hungry chips continuously and reliably.
  4. Networking and interconnect — the technology (from companies like Arista, Broadcom, Marvell) that links individual chips into servers and servers into massive clusters, since AI models today run across thousands of chips working in concert, not on a single chip alone.
  5. Software — the programming platforms, frameworks, and cloud services (Nvidia's CUDA, cloud platforms, AI frameworks) that let developers actually use all this hardware, and that often create durable competitive advantages independent of the hardware itself.
Software (CUDA, frameworks, cloud platforms) Networking (Arista, Broadcom, Marvell) Power, Cooling, Data Centers (Constellation, Vertiv) Chips: GPUs, ASICs, Memory (Nvidia, AMD, Micron, SanDisk) Manufacturing & Equipment (TSMC, ASML, Applied Materials, KLA, Lam)

Figure: The five layers of the AI infrastructure value chain, from foundational manufacturing at the bottom to user-facing software at the top. News about any one layer requires asking which companies in the other layers are affected, and how.

How the Layers Depend on Each Other

These layers are not independent — they are tightly interlocking. A chip design (layer 1) cannot exist without a foundry and equipment to manufacture it (layer 2). A finished chip is useless without power and cooling to run it (layer 3) and networking to connect it to thousands of other chips (layer 4). And none of it is usable by an actual business without software (layer 5) to program and orchestrate it. This is why a shift in one layer — say, a move toward liquid cooling because chips run hotter, or a shift in networking standards because clusters are growing larger — tends to ripple through the others. A change in chip power consumption directly affects cooling equipment demand; a change in cluster size directly affects networking architecture; a shift in chip design philosophy (GPU versus ASIC) directly affects which foundry packaging techniques are needed.

What This Course Does Not Cover

This course will not teach you how a transistor works, how to write code that runs on a GPU, or how to build a discounted cash flow model for these companies. It is deliberately conceptual: enough working vocabulary and structural understanding that when a company's earnings call mentions "CoWoS capacity," "HBM bit growth," or "scale-up versus scale-out networking," you understand what business dynamic is actually being discussed — and which companies in the value chain are the ones to watch as a result.

Reading the Rest of the Course

Each subsequent concept in this course drills into one node of this map in more depth: what the technology is, why it exists, which companies compete there, and what tends to drive demand or margin for that specific business. As you go, keep coming back to this five-layer map — it is the scaffolding that ties every individual concept back to the broader competitive and financial picture.

AI Infrastructure Fundamentals for Analysts — Qlaudia